1. Field of the Invention
The present invention relates to a wiring, which is used in, for example, a display device represented by a liquid crystal display device or a semiconductor device such as a ULSI, and to the method of manufacturing the same.
2. Description of the Related Art
In general, a wiring and an electrode, which are formed of aluminum (Al) or an alloy thereof, are used mainly in a semiconductor device represented by an LSI or a ULSI. However, copper (Cu) has an electrical resistance lower than that of Al and a high resistance to the electromigration and the stress migration. Such being the situation, the use of copper as the material of the wiring and the electrode of the next era is being studied in accordance with, for example, the progress of the miniaturization and the improvement in the operating speed which have been brought about as a result of the improvement in the degree of integration achieved in recent years.
Further, in the field of display devices represented by, for example, a liquid crystal display device, the demands for the wiring having a low electrical resistance as in the field of the semiconductor device have been enhanced by, for example, the increase in the wiring length accompanying the enlargement of the display area, and by the development of a monolithic device having various functions such as a driver circuit and a memory within a pixel mounted thereto.
It was difficult to achieve a fine processing of copper for forming a wiring by a simple combination of a masking technology utilizing PEP (Photo Engraving Process), which is called photolithography, with an etching technology such as RIE (Reactive Ion Etching). To be more specific, a copper halide has a vapor pressure markedly lower than that of aluminum halide and, thus, the copper halide is unlikely to be evaporated. Therefore, various problems are generated in the case of employing an etching technology such as RIE. For example, it is necessary to carry out the etching process under an atmosphere of 200 to 300° C. Also, it is necessary to prepare a mask formed of SiO2 or SiNx in place of the ordinary photoresist mask.
Such being the situation, it is possible to utilize a so-called “damascene process” disclosed in, for example, Japanese Patent Disclosure (Kokai) No. 2001-189295 and Japanese Patent Disclosure No. 11-135504. In the damascene process disclosed in these prior publications, a wiring groove having a desired wiring pattern is formed in advance in an insulator film formed on a substrate. Then, a thin copper layer is formed on the entire surface of the insulator film in a manner to fill the wiring groove by any of various methods such as a PVD (Physical Vapor Deposition) method utilizing a sputtering process, a metal plating method, and a CVD (Chemical Vapor Deposition) method utilizing an organometallic compound material. Further, a polishing process such as a CMP (Chemical Mechanical Polishing) process or an etch back process is applied to the thin copper layer until the insulator film positioned below the thin copper layer is exposed to the outside so as to form a wiring pattern formed of copper alone buried in the wiring groove.
However, the conventional technologies, including the technology disclosed in Japanese Patent Disclosure No. 2001-189295 and Japanese Patent Disclosure No. 11-135504 quoted above give rise to a serious problem, as pointed out below.
Specifically, the conventional damascene process quoted above requires at least a groove-forming step for forming a groove in which the wiring is buried, a film-forming step for forming a wiring pattern and a via (plug) for connecting the upper and lower electrodes, a photolithography step, an etching step, and a film-forming step for forming a polish-stopping film. It follows that the manufacturing process is rendered complex, which increases the manufacturing cost.
It should also be noted that, in order to lower the electrical resistance of the wiring, it is necessary to enlarge the cross sectional area of the wiring. However, in the case of employing a groove or a via hole having a large aspect ratio, i.e., having a small width or diameter and a large depth, in view of the limitation in the degree of integration, the burying nature of copper is lowered. Also, the CMP step included in the conventional damascene process, in which a thin copper film is formed on the entire surface of the substrate, followed by removing the undesired portion of the copper film, takes a log treating time so as to lower the throughput.
Further, a large CMP apparatus that permits processing a large semiconductor wafer having a diameter of 12 inches or more has been developed. However, a manufacturing apparatus has not yet been put to practical use when it comes to display devices using a glass substrate larger than the semiconductor wafer quoted above, and is not satisfactory in, for example, the surface flatness.
Also, in the case of a display device, e.g., a large substrate (display screen) mounted to a large liquid crystal display device, it is certainly possible to remove the undesired portion of the thin copper layer by the polishing of the entire surface utilizing the CMP process or by the etching. However, the area of the thin copper layer portion utilized as the wiring is very small, compared with the area of the glass substrate. In other words, most of the thin copper layer formed on the insulator film including the groove pattern is removed, and be discarded. It follows that the utilization efficiency of copper, which is a costly material, is very low, leading to a high manufacturing cost of the display device.